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ATMEGA128 Datasheet
8-bit Atmel Microcontroller
ATMEL Corporation
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ATMEGA128 pdf
SRAM Data
Memory
2467X–AVR–06/11
ATmega128
The Atmel® AVR® ATmega128 supports two different configurations for the SRAM data memory
as listed in Table 1.
Table 1. Memory Configurations
Configuration
Internal SRAM Data Memory External SRAM Data Memory
Normal mode
ATmega103 Compatibility
mode
4096
4000
up to 64K
up to 64K
Figure 9 shows how the ATmega128 SRAM Memory is organized.
The ATmega128 is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended
I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be
used. The Extended I/O space does not exist when the ATmega128 is in the ATmega103 com-
patibility mode.
In normal mode, the first 4352 Data Memory locations address both the Register file, the I/O
Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the
Register file, the next 64 location the standard I/O memory, then 160 locations of Extended I/O
memory, and the next 4096 locations address the internal data SRAM.
In ATmega103 compatibility mode, the first 4096 Data Memory locations address both the Reg-
ister file, the I/O Memory and the internal data SRAM. The first 32 locations address the Register
file, the next 64 location the standard I/O memory, and the next 4000 locations address the inter-
nal data SRAM.
An optional external data SRAM can be used with the ATmega128. This SRAM will occupy an
area in the remaining address locations in the 64K address space. This area starts at the
address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM
occupies the lowest 4352bytes in normal mode, and the lowest 4096bytes in the ATmega103
compatibility mode (Extended I/O not present), so when using 64Kbyte (65536 bytes) of Exter-
nal Memory, 61184bytes of External Memory are available in normal mode, and 61440 bytes in
ATmega103 compatibility mode. See “External Memory Interface” on page 25 for details on how
to take advantage of the external memory map.
When the addresses accessing the SRAM memory space exceeds the internal data memory
locations, the external data SRAM is accessed using the same instructions as for the internal
data memory access. When the internal data memories are accessed, the read and write strobe
pins (PG0 and PG1) are inactive during the whole access cycle. External SRAM operation is
enabled by setting the SRE bit in the MCUCR Register.
Accessing external SRAM takes one additional clock cycle per byte compared to access of the
internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP
take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine
calls and returns take three clock cycles extra because the two-byte program counter is pushed
and popped, and external memory access does not take advantage of the internal pipe-line
memory access. When external SRAM interface is used with wait-state, one-byte external
access takes two, three, or four additional clock cycles for one, two, and three wait-states
respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles
more than specified in the instruction set manual for one, two, and three wait-states.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file,
registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
18

ATMEGA128 Datasheet PDF


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