The CIOf pin controls whether the device data I/O pins
operate in the byte or word configuration. If the CIOf
pin is set at logic ‘1’, the device is in word configura-
tion, DQ15–DQ0 are active and controlled by CE# and
If the CIOf pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ7–DQ0 are
active and controlled by CE# and OE#. The data I/O
pins DQ14–DQ8 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 6–9 indicate the
address space that each sector occupies. The device
address space is divided into two banks: Bank 1 con-
tains the boot/parameter sectors, and Bank 2 contains
the larger, code sectors of uniform size. A “bank ad-
dress” is the address bits required to uniquely select a
bank. Similarly, a “sector address” is the address bits
required to uniquely select a sector.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
To read array data from the outputs, the system must
drive the CE#f and OE# pins to VIL. CE#f is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH. The CIOf pin determines
whether the device outputs array data in words or
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
See “Requirements for Reading Array Data” for more the WP#/ACC pin must not be left floating or uncon-
information. Refer to the AC Flash Read-Only Opera- nected; inconsistent behavior of the device may result.
tions table for timing specifications and to Figure 14 for
the timing diagram. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
Writing Commands/Command Sequences
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
To write a command or command sequence (which in- on DQ7–DQ0. Standard read cycle timings apply in
cludes programming data to the device and erasing this mode. Refer to the Autoselect Mode and Autose-
sectors of memory), the system must drive WE# and l e c t C o m m a n d S e q u e n c e s e c t i o n s f o r m o r e
CE#f to VIL, and OE# to VIH.
For program operations, the CIOf pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
The device features an Unlock Bypass mode to facil-
itate faster programming. Once a bank enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byte Configuration” section has details on pro-
gramming data to the device using both standard and
Unlock Bypass command sequences.
Simultaneous Read/Write Operations with
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being
erased). Figure 21 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. ICC6 and ICC7 in the DC Characteristics table
represent the current specifications for read-while-pro-
gram and read-while-erase, respectively.
November 12, 2001
DataSheet4 U .com