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ADC0804 Datasheet
8-Bit uP Compatible A/D Converters
National Semiconductor
National Semiconductor


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ADC0804 pdf
AC Electrical Characteristics (Continued)
The following specifications apply for VCC=5 VDC and TMINTATMAX unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max
COUT
TRI-STATE Output
Capacitance (Data Buffers)
5 7.5
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
VIN (1)
Logical “1” Input Voltage
(Except Pin 4 CLK IN)
VCC=5.25 VDC
2.0 15
VIN (0)
Logical “0” Input Voltage
(Except Pin 4 CLK IN)
VCC=4.75 VDC
0.8
IIN (1)
Logical “1” Input Current
(All Inputs)
VIN=5 VDC
0.005
1
IIN (0)
Logical “0” Input Current
(All Inputs)
VIN=0 VDC
−1 −0.005
CLOCK IN AND CLOCK R
VT+ CLK IN (Pin 4) Positive Going
Threshold Voltage
2.7 3.1 3.5
VT− CLK IN (Pin 4) Negative
Going Threshold Voltage
1.5 1.8 2.1
VH
VOUT (0)
CLK IN (Pin 4) Hysteresis
(VT+)−(VT−)
Logical “0” CLK R Output
Voltage
VOUT (1)
Logical “1” CLK R Output
Voltage
DATA OUTPUTS AND INTR
IO=360 µA
VCC=4.75 VDC
IO=−360 µA
VCC=4.75 VDC
0.6 1.3 2.0
0.4
2.4
VOUT (0)
Logical “0” Output Voltage
Data Outputs
INTR Output
VOUT (1)
VOUT (1)
IOUT
Logical “1” Output Voltage
Logical “1” Output Voltage
TRI-STATE Disabled Output
Leakage (All Data Buffers)
ISOURCE
ISINK
POWER SUPPLY
IOUT=1.6 mA, VCC=4.75 VDC
0.4
IOUT=1.0 mA, VCC=4.75 VDC
0.4
IO=−360 µA, VCC=4.75 VDC
2.4
IO=−10 µA, VCC=4.75 VDC
4.5
VOUT=0 VDC
−3
VOUT=5 VDC
3
VOUT Short to Gnd, TA=25˚C
4.5
6
VOUT Short to VCC, TA=25˚C
9.0
16
ICC Supply Current (Includes
Ladder Current)
fCLK=640 kHz,
VREF/2=NC, TA=25˚C
and CS =5V
ADC0801/02/03/04LCJ/05
1.1 1.8
ADC0804LCN/LCWM
1.9 2.5
Units
pF
VDC
VDC
µADC
µADC
VDC
VDC
VDC
VDC
VDC
VDC
VDC
VDC
VDC
µADC
µADC
mADC
mADC
mA
mA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.
Note 3: A zener diode exists, internally, from VCC to Gnd and has a typical breakdown voltage of 7 VDC.
Note 4: For VIN(−)VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct
for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high
level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows
50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct.
To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance
and loading.
Note 5: Accuracy is guaranteed at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be ex-
tended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.
Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The
start request is internally latched, see Figure 4 and section 2.0.
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