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ADC0804 Datasheet

8-Bit uP Compatible A/D Converters

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Functional Description (Continued)
2.2 Analog Differential Voltage Inputs and
Common-Mode Rejection
This A/D has additional applications flexibility due to the ana-
log differential voltage input. The VIN(−) input (pin 7) can be
used to automatically subtract a fixed voltage value from the
input reading (tare correction). This is also useful in 4 mA–20
mA current loop conversion. In addition, common-mode
noise can be reduced by use of the differential input.
The time interval between sampling VIN(+) and VIN(−) is 4-12
clock periods. The maximum error voltage due to this slight
time difference between the input voltage samples is given
by:
where:
Ve is the error voltage due to sampling delay
VP is the peak value of the common-mode voltage
fcm is the common-mode frequency
As an example, to keep this error to 14 LSB (5 mV) when
operating with a 60 Hz common-mode frequency, fcm, and
using a 640 kHz A/D clock, fCLK, would allow a peak value of
the common-mode voltage, VP, which is given by:
or
which gives
VP1.9V.
The allowed range of analog input voltages usually places
more severe restrictions on input common-mode noise lev-
els.
An analog input voltage with a reduced span and a relatively
large zero offset can be handled easily by making use of the
differential input (see section 2.4 Reference Voltage).
2.3 Analog Inputs
2.3 1 Input Current
Normal Mode
Due to the internal switching action, displacement currents
will flow at the analog inputs. This is due to on-chip stray ca-
pacitance to ground as shown in Figure 5.
DS005671-14
rON of SW 1 and SW 2 5 k
r=rON CSTRAY 5 kx 12 pF = 60 ns
FIGURE 5. Analog Input Impedance
The voltage on this capacitance is switched and will result in
currents entering the VIN(+) input pin and leaving the VIN(−)
input which will depend on the analog differential input volt-
age levels. These current transients occur at the leading
edge of the internal clocks. They rapidly decay and do not
cause errors as the on-chip comparator is strobed at the end
of the clock period.
Fault Mode
If the voltage source applied to the VIN(+) or VIN(−) pin ex-
ceeds the allowed operating range of VCC+50 mV, large in-
put currents can flow through a parasitic diode to the VCC
pin. If these currents can exceed the 1 mA max allowed
spec, an external diode (1N914) should be added to bypass
this current to the VCC pin (with the current bypassed with
this diode, the voltage at the VIN(+) pin can exceed the VCC
voltage by the forward voltage of this diode).
2.3.2 Input Bypass Capacitors
Bypass capacitors at the inputs will average these charges
and cause a DC current to flow through the output resis-
tances of the analog signal sources. This charge pumping
action is worse for continuous conversions with the VIN(+) in-
put voltage at full-scale. For continuous conversions with a
640 kHz clock frequency with the VIN(+) input at 5V, this DC
current is at a maximum of approximately 5 µA. Therefore,
bypass capacitors should not be used at the analog inputs or
the VREF/2 pin for high resistance sources (> 1 k). If input
bypass capacitors are necessary for noise filtering and high
source resistance is desirable to minimize capacitor size, the
detrimental effects of the voltage drop across this input resis-
tance, which is due to the average value of the input current,
can be eliminated with a full-scale adjustment while the
given source resistor and input bypass capacitor are both in
place. This is possible because the average value of the in-
put current is a precise linear function of the differential input
voltage.
2.3.3 Input Source Resistance
Large values of source resistance where an input bypass ca-
pacitor is not used, will not cause errors as the input currents
settle out prior to the comparison time. If a low pass filter is
required in the system, use a low valued series resistor
(1 k) for a passive RC section or add an op amp RC ac-
tive low pass filter. For low source resistance applications,
(1 k), a 0.1 µF bypass capacitor at the inputs will prevent
noise pickup due to series lead inductance of a long wire. A
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