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12-/14-/16-Bit nanoDAC

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Data Sheet
AD5620/AD5640/AD5660
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
t11
t2
t3
t4
t5
t6
t7
t8
t9
t10
Limit at TMIN, TMAX
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
50 33
13 13
13 13
13 13
55
4.5 4.5
00
50 33
13 13
00
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
SCLK
SYNC
DIN
t10 t1 t9
t8 t4
t3 t2 t7
MSB
t6
t5
LSB
LSB = DB0
MSB = DB23 FOR AD5660
MSB = DB15 FOR AD5620/AD5640
Figure 2. Serial Write Operation
Rev. G | Page 7 of 28
Analog Devices
Analog Devices


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