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(Datasheet) AD5660

12-/14-/16-Bit nanoDAC

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Data Sheet
POWER-ON RESET
The AD5620/AD5640/AD5660 family contains a power-on
reset circuit that controls the output voltage during power-up.
The AD5620/AD5640/AD5660-1-2 DAC output powers up to
0 V, and the AD5620/AD5660-3 DAC output powers up to
midscale. The output remains at this level until a valid write
sequence is made to the DAC, which is useful in applications
where it is important to know the state of the DAC output while
it is in the process of powering up.
POWER-DOWN MODES
The AD5620/AD5640/AD5660 have four separate modes of
operation. These modes are software-programmable by setting
two bits in the control register. Table 7 and Table 8 show how
the state of the bits corresponds to the operating mode of the
device.
Table 7. Modes of Operation for the AD5660
DB17
DB16
AD5660 Operating Mode
0 0 Normal operation
Power-down modes:
01
1 kΩ to GND
10
100 kΩ to GND
11
Three-state
Table 8. Modes of Operation for the AD5620/AD5640
DB15
DB14
AD5620/AD5640 Operating Mode
0 0 Normal operation
Power-down modes:
01
1 kΩ to GND
10
100 kΩ to GND
11
Three-state
When both bits are set to 0, the part works normally with its
normal power consumption of 550 µA at 5 V. However, for the
three power-down modes, the supply current falls to 480 nA
at 5 V (200 nA at 3 V). Not only does the supply current fall,
but the output stage is internally switched from the output of
the amplifier to a resistor network of known values. The advan-
tage is that the output impedance of the part is known while the
part is in power-down mode. There are three options: the out-
put is connected internally to GND through a 1 kΩ or a 100 kΩ
resistor, or it is left open-circuited (three-stated). The output
stage is shown in Figure 45.
AD5620/AD5640/AD5660
RESISTOR
STRING DAC
AMPLIFIER
VOUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 45. Output Stage During Power-Down
The bias generator, output amplifier, reference, resistor string,
and other associated linear circuitry are all shut down when
power-down mode is activated. However, the contents of the
DAC register are unaffected when in power-down. The time to
exit power-down is typically 5 µs for VDD = 5 V and VDD = 3 V
(see Figure 31).
MICROPROCESSOR INTERFACING
AD5660-to-Blackfin® ADSP-BF53x Interface
Figure 46 shows a serial interface between the AD5660 and the
Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multi-
processor communications. Using SPORT0 to connect to the
AD5660, the setup for the interface is as follows: DT0PRI drives
the DIN pin of the AD5660, while TSCLK0 drives the SCLK of
the part and SYNC is driven from TFS0.
ADSP-BF53x1
AD56601
TFS0
DTOPRI
TSCLK0
SYNC
DIN
SCLK
1 ADDITIONAL PINS OMITTED FOR CLARITY
Figure 46. AD5660-to-Blackfin ADSP-BF53x Interface
Rev. G | Page 19 of 28
Analog Devices
Analog Devices


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