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AD5660 Datasheet

12-/14-/16-Bit nanoDAC

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AD5620/AD5640/AD5660
Data Sheet
INPUT SHIFT REGISTER
AD5620/AD5640
The input shift register is 16 bits wide for the AD5620/AD5640
(see Figure 41 and Figure 42). The first two bits are control bits
that control which mode of operation the part is in (normal
mode or any of the three power-down modes). The next
14/12 bits, respectively, are the data bits. These are transferred
to the DAC register on the 16th falling edge of SCLK.
AD5660
The input shift register is 24 bits wide for the AD5660 (see
Figure 43). The first six bits are don’t care bits. The next two are
control bits that control which mode of operation the part is in
(normal mode or any of the three power-down modes). For a more
complete description of the various modes, see the Power-Down
Modes section. The next 16 bits are the data bits. These are
transferred to the DAC register on the 24th falling edge of SCLK.
DB15 (MSB)
SYNC INTERRUPT
In a normal write sequence for the AD5660, the SYNC line is
kept low for at least 24 falling edges of SCLK, and the DAC is
updated on the 24th falling edge. However, if SYNC is brought
high before the 24th falling edge, this acts as an interrupt to the
write sequence. The shift register is reset, and the write sequence
is seen as invalid. Neither an update of the DAC register contents
nor a change in the operating mode occurs (see Figure 44).
Similarly, in a normal write sequence for the AD5620/AD5640,
the SYNC line is kept low for at least 16 falling edges of SCLK,
and the DAC is updated on the 16th falling edge. However, if
SYNC is brought high before the 16th falling edge, this acts as
an interrupt to the write sequence.
DB0 (LSB)
PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
DB15 (MSB)
DATA BITS
Figure 41. AD5620 Input Register Contents
DB0 (LSB)
PD1 PD0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB23 (MSB)
DATA BITS
Figure 42. AD5640 Input Register Contents
DB0 (LSB)
X X X X X X PD1 PD0 D15 D14 D13 D12 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SCLK
DATA BITS
Figure 43. AD5660 Input Register Contents
SYNC
DIN MSB
LSB
MSB
LSB
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 16TH/24TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16TH/24TH FALLING EDGE
Figure 44. SYNC Interrupt Facility
Rev. G | Page 18 of 28
Analog Devices
Analog Devices


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