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AD5660 Datasheet

12-/14-/16-Bit nanoDAC

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Data Sheet
The AD5620/AD5640/AD5660 DACs are fabricated on a CMOS
process. The architecture consists of a string DAC followed by an
output buffer amplifier. The parts include an internal 1.25 V/2.5 V,
5 ppm/°C reference that is internally gained up by 2. Figure 39
shows a block diagram of the DAC architecture.
REF (+)
REF (–)
Figure 39. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
D is the decimal equivalent of the binary code that is loaded to
the DAC register.
0 to 4095 for AD5620 (12 bit)
0 to 16383 for AD5640 (14 bit)
0 to 65535 for AD5660 (16 bit)
N is the DAC resolution.
Figure 40. Resistor String
The resistor string section is shown in Figure 40. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
The AD5620/AD5640/AD5660-1 parts include an internal,
1.25 V, 5 ppm/°C reference, giving a full-scale output voltage of
2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an
internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output
voltage of 5 V. The reference associated with each part is
available at the VREFOUT pin. A buffer is required if the reference
output is used to drive external loads. It is recommended that a
100 nF capacitor is placed between the reference output and
GND for reference stability.
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. This output
buffer amplifier has a gain of 2 derived from a 50 kΩ resistor
divider network in the feedback path. The inverting input of the
output amplifier is available to the user, allowing for remote
sensing. This VFB pin must be connected to VOUT for normal
operation. It can drive a load of 2 kΩ in parallel with 1000 pF to
GND. Figure 22 shows the source and sink capabilities of the
output amplifier. The slew rate is 1.5 V/µs with a ¼ to ¾ full-
scale settling time of 10 µs.
The AD5620/AD5640/AD5660 have a 3-wire serial interface
(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as most DSPs.
See Figure 2 for a timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low.
Data from the DIN line is clocked into the 16-bit shift register
(AD5620/AD5640) or the 24-bit shift register (AD5660) on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5620/AD5640/AD5660 compatible
with high speed DSPs. On the 16th falling clock edge (AD5620/
AD5640) or the 24th falling clock edge (AD5660), the last data
bit is clocked in and the programmed function is executed, that
is, a change in the DAC register contents and/or a change in the
mode of operation is executed. At this stage, the SYNC line can
be kept low or be brought high. In either case, it must be brought
high for a minimum of 33 ns before the next write sequence so
that a falling edge of SYNC can initiate the next write sequence.
Because the SYNC buffer draws more current when VIN = 2 V
than it does when VIN = 0.8 V, SYNC should be idled low between
write sequences for even lower power operation of the parts. As
is mentioned previously, however, SYNC must be brought high
again just before the next write sequence.
Rev. G | Page 17 of 28
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