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AD5555 Datasheet
16-/14-Bit DACs
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AD5545/AD5555
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
RFBA 1
VREFA 2
IOUTA 3
AGNDA 4
AGNDB 5
IOUTB 6
VREFB 7
RFBB 8
AD5545/
AD5555
TOP VIEW
(Not to Scale)
16 CLK
15 LDAC
14 MSB
13 VDD
12 DGND
11 CS
10 RS
9 SDI
02918-0-002
Figure 4. 16-Lead TSSOP
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
1 RFBA
2 VREFA
3 IOUTA
4 AGNDA
5 AGNDB
6 IOUTB
7 VREFB
8 RFBB
9 SDI
10 RS
11 CS
12 DGND
13 VDD
14 MSB
15 LDAC
16 CLK
Description
Establish voltage output for DAC A by connecting this pin to an external amplifier output.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can
be tied to the VDD pin.
DAC A Current Output.
DAC A Analog Ground.
DAC B Analog Ground.
DAC B Current Output.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage.
This pin can be tied to the VDD pin.
Establish voltage output for DAC B by the RFBB pin connecting to an external amplifier output.
Serial Data Input. Input data loads directly into the shift register.
Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or midscale. Register
Data = 0x0000 when MSB = 0. Register Data = 0x8000 for AD5545 and 0x2000 for AD5555 when
MSB = 1.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register
data to the input register when CS/LDAC returns high. This does not affect LDAC operation.
Digital Ground Pin.
Positive Power Supply Input. Specified range of operation 5 V ± 10%.
MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on.
Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can also be tied
permanently to ground or VDD.
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC
registers. Asynchronous active low input. See Table 7 and Table 8 for operation.
Clock Input. Positive edge clocks data into shift register.
Rev. I | Page 6 of 23

AD5555 Datasheet PDF


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