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AD5555 Datasheet

16-/14-Bit DACs

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AD5545/AD5555
Data Sheet
Parameter
AC CHARACTERISTICS
Output Voltage Setting Time
Reference Multiplying BW
DAC Glitch Impulse
Feedthrough Error
Digital Feedthrough
Total Harmonic Distortion
Analog Crosstalk
Output Spot Noise Voltage
Symbol Conditions
tS
BW
Q
VOUT/VREF
Q
THD
CTA
eN
To ±0.1% full scale, data = zero scale to
full scale to zero scale
VREF = 100 mV rms, data = full scale, C1 = 5.6 pF
VREF = 0 V, data = midscale minus 1 to midscale
Data = zero scale, VREF = 100 mV rms,
f = 1 kHz, same channel
CS = logic high and fCLK = 1 MHz
VREF = 5 V p-p, data = full scale, f = 1 kHz to 10 kHz
VREFB = 0 V, measure VOUTB with VREFA = 5 V p-p
sine wave, data = full scale, f = 1 kHz to 10 kHz
f = 1 kHz, BW = 1 Hz
Min Typ Max Unit
0.5
6.9
–2
–81
7
–104
–95
12
µs
MHz
nV-s
dB
nV-s
dB
dB
nV/√Hz
1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP1177 I-to-V converter amplifier. The AD5545 RFB terminal
is tied to the amplifier output. Typical values represent average readings measured at 25°C.
2 These parameters are guaranteed by design and not subject to production testing.
3 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier and the AD8065 for the THD specification.
4 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
TIMING DIAGRAMS
SDI A1 A0 D15 D14 D13 D12 D11 D10
D1 D0
CLK
CS
LDAC
tCSS
tDS tDH
tCH tCL
Figure 2. AD5545 18-Bit Data Word Timing Diagram
INPUT REG LD
tCSH
tLDS
tLDH
tLDAC
02918-0-003
SDI
CLK
CS
LDAC
A1 A0 D13 D12 D11 D10 D09 D08
tCSS
tDS tDH
tCH tCL
Figure 3. AD5555 16-Bit Data Word Timing Diagram
Rev. I | Page 4 of 23
D1 D0
INPUT REG LD
tCSH
tLDS
tLDH
tLDAC
02918-0-004
Analog Devices
Analog Devices


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