Figure 21. Operational Compensation Capacitor for Gain Peaking
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited GBP, and if there
is excessive parasitic capacitance at the inverting node.
An optional compensation capacitor, C1, can be added for
stability as shown in Figure 21. C1 should be found empirically,
but 6 pF is generally more than adequate for the compensation.
The AD5545/AD5555 is inherently a 2-quadrant multiplying
DAC. It can easily be set up for unipolar output operation. The
full-scale output polarity is the inverse of the reference input
In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing. This
is easily accomplished by using an additional external amplifier,
U4, configured as a summing amplifier (see Figure 22). In this
circuit, the second amplifier, U4, provides a gain of 2, which
increases the output span magnitude to 5 V. Biasing the external
amplifier with a 2.5 V offset from the reference voltage results in a
full 4-quadrant multiplying circuit. The transfer equation of this
circuit shows that both negative and positive output voltages are
created because the input data (D) is incremented from code zero
(VOUT = −2.5 V) to midscale (VOUT = 0 V) to full scale (VOUT =
VOUT = (D/32,768 − 1) × VREF (AD5545)
VOUT = (D/8192 − 1) × VREF (AD5555)
For the AD5545, the external resistance tolerance becomes the
dominant error that users should be aware of.
5V VOUT VIN
–2.5 < VO < +2.5
Figure 22. Four-Quadrant Multiplying Application Circuit
Rev. I | Page 12 of 23