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AD5170 Datasheet

I2C Digital Potentiometer

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AD5170
TIMING CHARACTERISTICS: 2.5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD; VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter
I2C INTERFACE TIMING CHARACTERISTICS1 (SPECIFICATIONS
APPLY TO ALL PARTS)
SCL Clock Frequency
tBUF Bus Free Time Between Stop and Start
tHD;STA Hold Time (Repeated Start)
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Repeated Start Condition
tHD;DAT Data Hold Time2
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for Stop Condition
OTP Program Time
Symbol Conditions
fSCL
t1
t2 After this period, the first clock
pulse is generated
t3
t4
t5
t6
t7
t8
t9
t10
t11
1 See Figure 2 for locations of measured values.
2 The maximum tHD;DAT must be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Min Typ Max Unit
400 kHz
1.3 μs
0.6 μs
1.3
0.6
0.6
0.9
100
300
300
0.6
400
μs
μs
μs
μs
ns
ns
ns
μs
ms
Timing Diagram
SCL
t2
SDA
t1
PS
t8 t6 t9
t3
t8 t9
t4
t7
t2
t5
S
Figure 2. I2C Interface Detailed Timing Diagram
t10
P
Rev. G | Page 7 of 24
Analog Devices
Analog Devices


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