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AD5170 Datasheet
I2C Digital Potentiometer
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AD5170
Parameter
POWER SUPPLIES
Power Supply Range
OTP Supply Voltage8, 9
Supply Current
OTP Supply Current8, 10, 11
Power Dissipation12
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS13
–3 dB Bandwidth
Total Harmonic Distortion
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
Resistor Noise Voltage Density
Symbol
VDD RANGE
VDD_OTP
IDD
IDD_OTP
PDISS
PSS
BW
THDW
tS
eN_WB
Conditions
Min
VIH = 5 V or VIL = 0 V
VDD_OTP = 5 V, TA = 25°C
VIH = 5 V or VIL = 0 V, VDD = 5 V
VDD = 5 V ± 10%, code =
midscale
2.7
5.6
RAB = 10 kΩ, code = 0x80
RAB = 50 kΩ, code = 0x80
RAB = 100 kΩ, code = 0x80
VA =1 V rms, VB = 0 V, f = 1 kHz,
RAB = 10 kΩ
VA = 5 V, VB = 0 V, ±1 LSB error
band
RWB = 5 kΩ, f = 1 kHz
Typ1 Max
5.7
3.5
100
±0.02
5.5
5.8
6
33
±0.08
600
100
40
0.1
2
9
Unit
V
V
μA
mA
μW
%/%
kHz
kHz
kHz
%
μs
nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up
to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-
up resistors.
9 Different from operating power supply, power supply OTP is used one time only.
10 Different from operating current, supply current for OTP lasts approximately 400 ms for use one time only.
11 See Figure 26 for the energy plot during OTP program.
12 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
13 All dynamic characteristics use VDD = 5 V.
Rev. G | Page 6 of 24

AD5170 Datasheet PDF


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