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AD5162 Datasheet

SPI Digital Potentiometer

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AD5162
TEST CIRCUITS
Figure 27 through Figure 32 illustrate the test circuits that define the test conditions used in the product specification tables (see Table 1
and Table 2).
DUT
A
W
V+
B
V+ = VDD
1LSB = V+/2N
VMS
VA
DUT
V+ VDD A W
B
V+ = VDD ± 10%
( )PSRR (dB) = 20 LOG
PSS
(%/%)
=
VMS%
VDD%
VMS
VDD
VMS
Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error
(INL, DNL)
Figure 30. Test Circuit for Power Supply Sensitivity
(PSS, PSSR)
NO CONNECT
DUT
AW
B
IW
VMS
Figure 28. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation: R-INL, R-DNL)
VMS2
DUT
A
W
B
IW = VDD/RNOMINAL
VW
RW = [VMS1 – VMS2]/IW
VMS1
Figure 29. Test Circuit for Wiper Resistance
VIN
OFFSET
GND
2.5V
DUT
AW
B
+15V
AD8610
–15V
VOUT
Figure 31. Test Circuit for Gain vs. Frequency
NC
DUT
VDD
A
W
GND B
ICM
VCM
NC NC = NO CONNECT
Figure 32. Test Circuit for Common-Mode Leakage Current
Rev. C | Page 12 of 20
Analog Devices
Analog Devices



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