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AD5160 Datasheet

256-Position SPI-Compatible Digital Potentiometer

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Data Sheet
AD5160
TIMING CHARACTERISTICS—ALL VERSIONS
VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter
SPI INTERFACE TIMING CHARACTERISTICS1, 2
Clock Frequency
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS Setup Time
CS High Pulse Width
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
Symbol
fCLK
tCH, tCL
tDS
tDH
tCSS
tCSW
tCSH0
tCSH1
Conditions
Specifications apply to all parts
Clock level high or low
Min
20
5
5
15
40
0
0
Typ1 Max
25
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
1 See the timing diagram, Figure 38, for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a
voltage level of 1.5 V.
2 Guaranteed by design and not subject to production test.
Rev. C | Page 5 of 16
Analog Devices
Analog Devices



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