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80960CA-16 Datasheet


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80960CA-16 pdf
 Two Instructions Clock Sustained Execution
 Four 59 Mbytes s DMA Channels with Data Chaining
 Demultiplexed 32-bit Burst Bus with Pipelining
Y 32-bit Parallel Architecture
Two Instructions clock Execution
Load Store Architecture
Sixteen 32-bit Global Registers
Sixteen 32-bit Local Registers
Manipulates 64-bit Bit Fields
11 Addressing Modes
Full Parallel Fault Model
Supervisor Protection Model
Y Fast Procedure Call Return Model
Full Procedure Call in 4 Clocks
Y On-Chip Register Cache
Caches Registers on Call Ret
Minimum of 6 Frames Provided
Up to 15 Programmable Frames
Y On-Chip instruction Cache
1 Kbyte Two-Way Set Associative
128-bit Path to instruction Sequencer
Cache-Lock Modes
Cache-Off Mode
Y High Bandwidth On-Chip Data RAM
1 Kbyte On-Chip Data RAM
Sustains 128 bits per Clock Access
Y Four On-Chip DMA Channels
59 Mbytes s Fly-by Transfers
32 Mbytes s Two-Cycle Transfers
Data Chaining
Data Packing Unpacking
Programmable Priority Method
Y 32-Bit Demultiplexed Burst Bus
128-bit internal Data Paths to and
from Registers
Burst Bus for DRAM Interfacing
Address Pipelining Option
Fully Programmable Wait States
Supports 8- 16- or 32-bit Bus Widths
Supports Unaligned Accesses
Supervisor Protection Pin
Y Selectable Big or Little Endian Byte
Y High-Speed Interrupt Controller
Up to 248 External interrupts
32 Fully Programmable Priorities
Multi-mode 8-bit Interrupt Port
Four internal DMA Interrupts
Separate Non-maskable interrupt Pin
Context Switch in 750 ns Typical
Y Product Grades Available
SE3 b40 C to a110 C
December 1994
Order Number 271327-001
Intel Corporation
Intel Corporation

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