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80321 Datasheet

I/O Processor

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Intel® 80321 I/O Processor
Datasheet
Product Features
s Core Features
s DMA Controller
— Integrated Intel® XScaleCore
— Two Independent Channels Connected
— ARM* V5T Instruction Set
— ARM V5E DSP Extensions
— 400 MHz and 600 MHz
— Write Buffer, Write-back Cache
to Internal Bus
— Up to 1064 MB/s Burst Support in
PCI-X Mode
— Up to 1600 MB/s Burst Support for
Internal Bus
s PCI Bus Interface
— Two 1-KB Queues in Ch-0 and Ch-1
PCI Local Bus Specification, Rev. 2.2
compliant
— 232 Addressing Range on Internal Bus
Interface
PCI-X Addendum to the PCI Local Bus
— 264 Addressing Range on PCI Interface
Specification, Rev. 1.0a
s Application Accelerator Unit
— 64-bit/66MHz Operation in PCI Mode
— Performs XOR on Read Data
—64-bit/133MHz Operation in PCI-X Mode — Compute Parity Across Local Memory
— Support 32-bit PCI Initiators and Targets
Blocks
— Four Split Read Requests as Initiator
— Eight Split Read Requests as Target
— 64-bit Addressing Support
— 1 KB/512-byte Store Queue
s I2C Bus Interface Units
— Two Separate I2C Units
s Memory Controller
— Serial Bus
—PC200 Double Data Rate (DDR) SDRAM — Master/Slave Capabilities
— Up to 1 GB of 64-bit DDR SDRAM
— System Management Functions
— Up to 512 MB of 32-bit DDR SDRAM s SSP Serial Port
— Single-bit Error Correction, Multi-bit
Support (ECC)
— Full-duplex Synchronous Serial Interface
— Supports 7.2 KHz to 1.84 MHz Bit Rates
— 1024-byte Posted Memory Write Queue s Peripheral Performance Monitoring Unit
— 40- and 72-bit wide Memory Interface
— One Dedicated Global Time Stamp
Counter
s Address Translation Unit
— Fourteen Programmable Event Counters
— 2 KB or 4 KB Outbound Read Queue
— Three Control/Status Registers
— 4 KB Outbound Write Queue
s Timers
— 4 KB Inbound Read and Write Queue
— Two Dual-programmable 32-bit Timers
—Connects Internal Bus to PCI/PCI-X Bus — Watchdog Timer
s 544-Ball, Plastic Ball Grid Array (PBGA)
s Eight General Purpose I/O Pins
Document Number: 273518-002
June 2002
Intel
Intel



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